1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and more particularly, to a method of forming a flat surface of an insulator film of a semiconductor device containing a polishing process, which is applicable for multilayer interconnection of the semiconductor device.
2. Description of the Prior Art
FIGS. 1A and 1D show a conventional method of forming a flat surface of an insulator film of a semiconductor device, which is disclosed in the Japanese Non-Examined Patent Publication No. 62-216344.
First, as shown in FIG. 1A, a first insulator film 42 of silicon dioxide (SiO.sub.3) is formed on the surface of a silicon (Si) substrate 41. Then, a first wiring film 53 is formed on the first insulator film 42 to be patterned to a given shape.
Next, an interlayer insulator film 51 of phosphor-silicate glass (PSG) is formed on the first wiring film 53 patterned. The first interlayer insulator film 51 is in contact with the first insulator film 42 at the positions where the first wiring film 53 does not exist.
Subsequently, a polishing stopper film 52 of silicon nitride (Si.sub.3 N.sub.4) is formed on the first interlayer insulator film 51 by a plasma-enhanced chemical vapor deposition (CVD) method and then, a plurality of through holes 49 are formed to pass through the polishing stopper film 52 and the first interlayer insulator film 51 by a popular technique such as photolithography and etching. The through holes 49 reach the surface of the first wiring film 53, respectively.
Next, as shown in FIG. 15, a conductive film 54 of aluminum (Al) for interconnection is formed on the polishing stopper film 52 by a sputtering method. The conducive film 54 thus formed is in contact with the first wiring film 53 through the through holes 49 at different positions.
The first conductive film 54 for interconnection is polished until the polishing stopper film 52 disposed thereunder is exposed. Thus, as shown in FIG. 1C, the conductive film 54 is left in the respective through holes 49, in other words, the remainder of the conductive film 54 is buried in the respective through holes 49.
Then, a second wiring film 50 is formed on the polishing stopper film 52, and as a result, the second wiring film 50 is interconnected with the first wiring film 53 through the remainder of the first conductive film 54 in the through holes 49.
Thereafter, the second wiring film 50 is patterned to a given shape as required.
As described above, with the conventional method, the Al film 54 is removed by the polishing process, and a flatter surface of the second wiring film 50 is obtained by utilizing a low polishing rate of Si.sub.3 N.sub.4 as the polishing stopper film 52.
Therefore, there is a problem that waste Al, which is difficult to remove, is produced during the polishing process. In detail, the Al film 54 is not sufficiently chemical-resistant, so that any chemicals having supreme washing effects cannot be used therefor.
In addition, due to softness, the Al film 54 can easily be polished excessively and the remaining Al film 54 in the through holes 49 can easily be injured or damaged during the washing process.
There is another problem in that the surface of the interlayer insulator film 51 cannot be flattened extensively because the Si.sub.3 N.sub.4 film 52 as the polishing stopper is formed on the interlayer insulator film 51.